1. Field of the Invention
The present invention relates to improvement of the characteristics of a field effect transistor (FET) of a metal-insulator-semiconductor transistor (MIS) structure.
2. Conventional Art
MOSFETs which are most widely used among the MISFETs formed in integrated circuits have an active region defined by a device isolation region, and a gate electrode formed over the active region. A source and a drain are formed in the active region, on respective sides of the gate electrode, and the part of the active region between the source and the drain constitute the channel.
A discussion on the performance of MOSFETs is given in the following publication No. 1:
Publication No. 1: MOS Scaling: Transistor Challenges for the 21st Century, Scott Thompson, et al. (Intel Technology Journal Q3'98).
Problems encountered in the development of MOSFETs are described in the following publication No. 2:
Publication No. 2: International Technology Roadmap for Semiconductors, 2001 Edition, “Process Integration, Devices, and Structures and Emerging Research Devices” (available from ITRS Web Site).
The power consumption during stand-by of a MISFET depends on the off-current value (Ioff), while the operating speed of the circuit depends on the on-current value (Ion). It is therefore desirable that the off-current value (Ioff) be smaller, and the on-current value be larger. The ratio of the on-current value to the off-current value (Ion/Ioff ratio) can be improved to a certain degree, up to a certain limit, by optimizing the channel profile and drain profile, in a specific technology node corresponding to specific minimum values of the gate length and the gate oxide thickness. In order to improve the performance further, it is necessary to advance to a next technology node, to reduce the gate length and the gate oxide thickness. However, the size reduction is associated with increase in gate leak current, and degradation in the gate oxide reliability. It will therefore be necessary to lower the power supply voltage. As a result, in a small-sized transistors, it is considered that, with advancement of the technology node, the same Ion/Ioff ratio can be realized at best, with a lower voltage. See for example Publication No. 2, in particular FIG. 36a, in which “Nominal LOP NMOS sub-threshold leakage current” corresponds to Ioff, while “Nominal LOP NMOS Saturation drive current” corresponds to Ion. It is seen that the former tends to increase from 100 pA/μm, while the latter is kept constant at about 600 μA/μm, indicating that the performance is not improved with the technology advancement and the chip size reduction.